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  <url><loc>https://hdlbits.com/problems/verilog-language/basics/xnor-gate</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/adder-1</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/adder-2</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/adder-subtractor</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/carry-select-adder</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/connect-ports-name</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/connect-ports-position</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/instantiate-by-name</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/instantiate-multiple</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/intermediate-wire</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/modules</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/modules-vectors</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/ripple-carry-adder</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/three-modules</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/modules-hierarchy/two-submodule-types</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/generate-100bit-adder</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/generate-100digit-bcd</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/generate-bcd-adder</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/generate-xor-ring</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/parity-reduction</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/popcount-255</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/reduction-wide</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/ternary-mux4</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/more-features/vector-reversal-100bit</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/avoid-latches</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/case-decoder</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/case-mux</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/clocked-register</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/combinational-process</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/complete-case</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/conditional-mux</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/min-max</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/popcount-for-loop</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/priority-encoder</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/priority-encoder-casez</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/procedures/transparent-latch</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/bit-reversal</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/byte-select</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/concat-replicate</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/four-input-gates</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/more-replication</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/replication-operator</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/replication-sign</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/sign-extend</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/vector-bitwise</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/vector-concatenation</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/vector-details</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/vector-part-select</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/vector-passthrough</loc></url>
  <url><loc>https://hdlbits.com/problems/verilog-language/vectors/vector-reversal</loc></url>
</urlset>
