Build a 2-to-1 multiplexer, but instead of using an assign statement or a ternary operator, build it structurally out of basic gates (AND, OR, NOT).
When sel is 0, out should follow a. When sel is 1, out should follow b.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
a |
input | 1 | Data input, selected when sel = 0 |
b |
input | 1 | Data input, selected when sel = 1 |
sel |
input | 1 | Select line |
out |
output | 1 | Selected output |
Truth table
| sel | out |
|---|---|
| 0 | a |
| 1 | b |
The classic gate-level implementation is the AND-OR-INVERT form:
out = (~sel & a) | (sel & b)Instantiate and, or, and not gate primitives to implement this equation rather than writing a single continuous assignment.
In VHDL, the output port is named outp because out is a reserved keyword.