Browse Problems

First Steps

A Single Wire

Four Independent Wires

Inverter (NOT Gate)

2-Input AND Gate

Verilog Language

Basics

Constant One Output

Constant Vector Output

2-to-1 Multiplexer

Half Adder

Full Adder

Vectors

Vector Passthrough

8-bit Vector Bit Reversal

Byte Select from a 32-bit Word

Concatenation and Replication

Sign Extension

Modules: Hierarchy

Instantiate a Submodule by Name

Instantiate Multiple Copies of a Submodule

Connecting Submodules with an Intermediate Wire

4-bit Ripple-Carry Adder from Full Adders

Combining Two Different Submodule Types

Procedures

Priority Encoder (if/else)

3-to-8 Decoder (case statement)

Population Count (for loop)

Min/Max of Four Values

More Features

4-to-1 Mux with the Ternary Operator

Parity Generator (reduction operators)

Parameterized XOR Ring (generate)

Circuits

Combinational Logic

2-to-1 Multiplexer (Gate-Level)

4-to-1 Multiplexer

BCD to 7-Segment Display Decoder

4-bit Priority Encoder

K-Map Simplification: Prime BCD Digit Detector

8-bit Magnitude Comparator

4-bit Barrel Shifter (Rotate Left)

Sequential Logic

SR Latch (Gate-Level)

D Flip-Flop with Asynchronous Reset

D Flip-Flop with Synchronous Reset and Enable

4-bit Up/Down Counter

Decade (Mod-10) Counter

Universal Shift Register

Moore FSM: Non-Overlapping Sequence Detector (1011)

Mealy FSM: Overlapping Sequence Detector (1011)

Building Larger Circuits

4-bit ALU

Traffic Light Controller

Simple Datapath: Register File + ALU + Writeback

UART-Lite Transmitter

Parameterized Fixed-Priority Arbiter

Verification

Reading Simulations

Identify the Gate

Infer the Counter

Infer the Mux

Infer the Edge Detector

Writing Testbenches

Exhaustively Test a Full Adder

Verify a Counter's Sequence

Verify an FSM's Output Sequence

Verify a Shift Register

RTL Design Patterns

FIFOs

Synchronous FIFO

Asynchronous FIFO (Dual-Clock, Gray-Coded Pointers)

Circular Buffer (Overwrite-on-Full)

FIFO with Almost-Full Flag

FIFO with Almost-Empty Flag

Clock Domain Crossing

2-Flop Synchronizer

Pulse Synchronizer

Toggle Synchronizer

Handshake Synchronizer (4-Phase Req/Ack)

Handshaking

Valid/Ready Interface Basics

Ready/Valid Pipeline Stage

Skid Buffer

Backpressure-Aware FIFO-Fed Pipeline

Pipelines

2-Stage Pipeline

4-Stage Pipeline

Pipelined Multiplier

Pipelined Adder (Carry-Select, 2-Stage)

Latency Matching with Shift Registers

Memories

Synchronous ROM

Single-Port RAM

Dual-Port RAM

Register File (2 Read Ports, 1 Write Port)

External SRAM Controller