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Verilog · SystemVerilog · VHDL

Learn digital design by writing it.

Practice HDL circuits from your first wire to production RTL — synchronous and asynchronous FIFOs, clock-domain-crossing synchronizers, valid/ready pipelines, and memory controllers. Everything compiles and simulates instantly, right in your browser.

Start with your first circuitExplore RTL patterns
module top_module (
    input  wire clk,
    input  wire rst_n,
    input  wire wr_en,
    input  wire [7:0] din,
    output reg  [7:0] dout,
    output wire full,
    output wire empty
);
    // synchronous FIFO — your move
endmodule
3

HDLs: Verilog, SystemVerilog & VHDL

5

Curriculum tracks, language to RTL

24+

Production RTL patterns (FIFOs, CDC, pipelines...)

0

Accounts required to start practicing

Built to be better than a Verilog-only wiki.

Three languages, one judge

Solve the same circuit in Verilog, SystemVerilog, or VHDL — pick the HDL your course or job actually uses.

Simulation runs in your browser

No server queue, no waiting. Your code compiles and simulates locally the moment you hit Run.

Real feedback, not just pass/fail

See a signal-level waveform and diff against the expected output — understand why a test failed, not just that it did.

Beyond the classroom

A dedicated RTL Design Patterns track covers FIFOs, clock-domain crossing, handshaking, pipelines, and memories — the blocks you'll actually build on the job.

Pick a track

From your first assigned wire to clock-domain crossing you'll be asked about in an interview.

Getting Started

Your first modules — wiring, ports, and how a submission gets checked.

First Steps

Verilog Language

The language fundamentals: wires, vectors, modules, procedural code.

BasicsVectorsModules: HierarchyProceduresMore Features

Circuits

Combinational and sequential building blocks, from gates to state machines.

Combinational LogicSequential LogicBuilding Larger Circuits

Verification

Reading waveforms and writing the testbenches that drive them.

Reading SimulationsWriting Testbenches

RTL Design Patterns

Production-grade blocks you will actually build on the job — not in any textbook problem set.

FIFOsClock Domain CrossingHandshakingPipelinesMemories

Your next FIFO won't design itself.

Jump into the problem set and start writing RTL — no signup required.

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