Build a minimal single-instruction datapath: an 8-entry, 8-bit register file with two combinational read ports feeding an ALU, and a synchronous write-back port. This models the core of one instruction slot in a simple processor.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous reset — clears all 8 registers to 0 |
rs1_addr |
input | 3 | Register file read address, port 1 |
rs2_addr |
input | 3 | Register file read address, port 2 |
rd_addr |
input | 3 | Register file write address |
reg_write |
input | 1 | Write enable for the writeback |
alu_op |
input | 3 | ALU opcode: 000=add, 001=sub, 010=and, 011=or, 100=xor |
imm |
input | 8 | Immediate value, for direct loads |
imm_src |
input | 1 | 1 = write imm to rd, 0 = write the ALU result to rd |
rs1_data |
output | 8 | Combinational read of regfile[rs1_addr] |
rs2_data |
output | 8 | Combinational read of regfile[rs2_addr] |
alu_result |
output | 8 | rs1_data OP rs2_data, combinational |
Behavior
- Reads are purely combinational:
rs1_dataandrs2_dataalways reflect the current contents of the addressed registers. - The ALU is purely combinational, operating on
rs1_dataandrs2_dataperalu_op(same opcode map as a standalone 4-bit ALU, but 8 bits wide here). - The writeback is synchronous: on each rising edge of
clk, ifreg_writeis asserted,regfile[rd_addr]is loaded with eitherimm(ifimm_src = 1) oralu_result(ifimm_src = 0). resetsynchronously clears every register to 0, taking priority overreg_write.
Since there is no separate immediate-load port, use imm_src to seed registers with known values (e.g. to set up test data) before exercising the ALU path.