Build the transmit shift-out logic of a UART, given an externally generated one-cycle tick pulse that arrives once per baud period (the baud-rate generator itself is out of scope — you are only given its output pulse).
A UART frame is: one start bit (0), 8 data bits (LSB first), then one stop bit (1). The line idles high between frames.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous reset to idle |
tick |
input | 1 | One-cycle pulse, once per baud period |
start |
input | 1 | One-cycle pulse requesting transmission of data |
data |
input | 8 | Byte to transmit (only sampled when accepted) |
tx |
output | 1 | Serial output line |
busy |
output | 1 | High while a frame is being transmitted |
Behavior
- While idle (
busy = 0),txis held high. Astartpulse latchesdataand begins a new frame;startis ignored whilebusyis already high. - Once a frame begins, each
tickpulse advances the transmitter by exactly one bit period: start bit, thendata[0],data[1], …,data[7], then the stop bit — ten bit periods in total. - After the stop bit’s
tick, the transmitter returns to idle (busy = 0,tx = 1) and is ready to accept the nextstart.
tick is generated externally at a fixed rate (e.g. once every N clock cycles for a given baud rate) — this circuit only needs to react to it, not generate it.