Build a Moore finite state machine that detects the bit sequence 1011 arriving one bit per clock cycle on in. When a match completes, y is high for the cycle in which the FSM occupies the accepting state.
This detector is non-overlapping: once a match completes, the search restarts from scratch on the next bit — even if the trailing bits of the just-completed match could also serve as the start of a new match.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous reset to the initial state |
in |
input | 1 | Serial input bit, one per clock |
y |
output | 1 | High while the FSM is in the “matched” state |
State diagram (state, input) -> next state
| State | Meaning | in=0 -> | in=1 -> | y (output) |
|---|---|---|---|---|
| S0 | no progress | S0 | S1 | 0 |
| S1 | matched “1” | S2 | S1 | 0 |
| S2 | matched “10” | S0 | S3 | 0 |
| S3 | matched “101” | S2 | S4 | 0 |
| S4 | matched “1011” | S0 | S1 | 1 |
Because this is a Moore machine, y depends only on the current state — it does not change mid-cycle when in changes. Note that the transitions out of S4 are identical to the transitions out of S0: after a match, the FSM behaves exactly as if it were starting over, discarding any possible overlap with the pattern just matched.