Sequential Logic

SR Latch (Gate-Level)

Build a cross-coupled NOR SR latch and reason about its set/reset/hold/invalid behavior.

D Flip-Flop with Asynchronous Reset

A D flip-flop that samples d on the rising clock edge, with an asynchronous active-high reset.

D Flip-Flop with Synchronous Reset and Enable

A D flip-flop with a synchronous, active-high reset that takes priority over a clock-enable input.

4-bit Up/Down Counter

A 4-bit counter that increments or decrements each clock, with a synchronous reset and free-running wraparound.

Decade (Mod-10) Counter

A synchronous-reset counter that cycles through 0-9 and wraps back to 0, rather than the full 4-bit range.

Universal Shift Register

A 4-bit register that can hold, parallel-load, shift left, or shift right, selected by a mode input.

Moore FSM: Non-Overlapping Sequence Detector (1011)

A Moore-style FSM that flags each non-overlapping occurrence of the bit pattern 1011 in a serial input stream.

Mealy FSM: Overlapping Sequence Detector (1011)

A Mealy-style FSM that flags every occurrence of the bit pattern 1011 in a serial input stream, including overlapping matches.