Build a 4-bit universal shift register with a synchronous, active-high reset. On each rising edge of clk, mode selects one of four operations.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous, active-high reset to 0 |
mode |
input | 2 | Operation select (see table) |
d |
input | 4 | Parallel load data |
sin_left |
input | 1 | Serial input for left shifts |
sin_right |
input | 1 | Serial input for right shifts |
q |
output | 4 | Register contents |
Mode encoding
| mode | Operation | Next q |
|---|---|---|
| 00 | Hold | q (unchanged) |
| 01 | Parallel load | d |
| 10 | Shift left | {q[2:0], sin_left} — sin_left enters the LSB, q[3] shifts out |
| 11 | Shift right | {sin_right, q[3:1]} — sin_right enters the MSB, q[0] shifts out |
reset overrides mode and forces q to 0000 on the next clock edge.