Build an SR latch out of two cross-coupled NOR gates — the classic gate-level memory element.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
s |
input | 1 | Active-high set |
r |
input | 1 | Active-high reset |
q |
output | 1 | Latch output |
qn |
output | 1 | Complementary output |
Behavior
| s | r | q (next) | qn (next) |
|---|---|---|---|
| 0 | 0 | hold (no change) | hold (no change) |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 (invalid: both outputs forced low) |
The circuit is two nor gates whose outputs feed back into each other’s inputs:
q = nor(r, qn)
qn = nor(s, q)s = r = 1 is an invalid input combination for an SR latch (it violates q = ~qn), but for these cross-coupled NOR gates it is still well-defined combinationally: both outputs are forced to 0 regardless of prior state. Avoid releasing both s and r to 0 directly from that state in the same step — which input leaves first (a race condition) is not something this circuit can resolve deterministically.