Now combine two inputs. A 2-input AND gate outputs 1 only when both of its inputs are 1; otherwise it outputs 0.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
a |
input | 1 | First operand |
b |
input | 1 | Second operand |
out |
output | 1 | Must always equal a & b |
Truth table
a |
b |
out |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Notes
- Use the bitwise AND operator:
&in Verilog/SystemVerilog,andin VHDL. - The VHDL output port is named
yinstead ofout, sinceoutis a reserved keyword in VHDL.