Your first logic gate. A NOT gate (inverter) outputs the opposite of its input: 0 becomes 1, and 1 becomes 0.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
in |
input | 1 | The bit to invert |
out |
output | 1 | Must always equal ~in |
Truth table
in |
out |
|---|---|
| 0 | 1 |
| 1 | 0 |
Notes
- Use the bitwise NOT operator:
~in Verilog/SystemVerilog,notin VHDL. - The VHDL port names are
in_bit/out_bitsinceinandoutare reserved keywords in VHDL.