A module can have as many ports as you like, and they don’t need to interact at all. Here you have four separate single-bit inputs and four separate single-bit outputs — each output just copies one input.
This is a good place to practice declaring multiple ports and multiple independent assignments in one module.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
a |
input | 1 | Copied to w |
b |
input | 1 | Copied to x |
c |
input | 1 | Copied to y |
d |
input | 1 | Copied to z |
w |
output | 1 | Must always equal a |
x |
output | 1 | Must always equal b |
y |
output | 1 | Must always equal c |
z |
output | 1 | Must always equal d |
Notes
- There is no interaction between the four pairs —
wdepends only ona,xonly onb, and so on. - Four separate
assignstatements (or a single concurrent assignment on a concatenated signal) both work.