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RTL Design Patterns/FIFOs

FIFO with Almost-Full Flag

medium
fifoalmost-fullbackpressureflow-control

Why you need this in addition to full

A plain full flag tells an upstream producer “stop right now” — but by the time that signal propagates back through a register stage or two, or by the time the producer’s own pipeline can actually react and stop issuing, one or two more words may already be in flight. If the producer only reacts to full, those in-flight words get dropped or corrupt the FIFO.

almost_full solves this by asserting early, with enough margin (ALMOST_FULL_THRESHOLD entries of headroom) to absorb whatever pipeline latency exists between the producer seeing the flag and actually stopping. This is exactly how flow control works in real bus fabrics and PCIe/Ethernet credit-based schemes: the “stop” signal is asserted with a safety margin sized to the round-trip latency of the flow-control loop.

Interface

Signal Direction Description
ALMOST_FULL_THRESHOLD parameter Number of free slots remaining when almost_full should assert.
wr_en / wr_data input Write port, same semantics as the basic Synchronous FIFO.
rd_en / rd_data input/output Read port, same fall-through semantics as the basic Synchronous FIFO.
full output High when the FIFO holds exactly DEPTH entries.
almost_full output High when occupancy >= DEPTH - ALMOST_FULL_THRESHOLD.
empty output High when the FIFO holds zero entries.

Correctness constraints

  • almost_full must assert exactly ALMOST_FULL_THRESHOLD entries before full would — no later (or a producer with that much in-flight latency will overflow the FIFO) and no meaningfully earlier (or you waste buffer capacity).
  • full implies almost_full (i.e. almost_full must already be high by the time the FIFO is completely full) — a design where full can assert while almost_full is still low is broken.
  • 0 <= ALMOST_FULL_THRESHOLD <= DEPTH must hold; the flag logic should not rely on write/read enables from the current cycle (only on the registered occupancy), so it settles cleanly without combinational loops.
  • All of the base Synchronous FIFO’s correctness constraints (no full+empty overlap, dropped writes while full, dropped reads while empty, strict ordering) still apply.