Track
RTL Design Patterns
Production-grade blocks you will actually build on the job — not in any textbook problem set.
FIFOs
5 problemsSynchronous and asynchronous FIFOs, circular buffers, almost-full/empty flags.
Clock Domain Crossing
4 problems2-flop, pulse, toggle, and handshake synchronizers.
Handshaking
4 problemsValid/ready protocols, skid buffers, backpressure.
Pipelines
5 problemsStaged datapaths, pipelined arithmetic, latency matching.
Memories
5 problemsROMs, single/dual-port RAM, register files, SRAM controllers.
Branch Prediction
4 problemsSaturating counters, global history, and a gshare predictor.