A circuit watches a single input, in, and pulses its output, out, high for exactly one cycle every time in rises from 0 to 1. A trace was captured across ten cycles, including one initial cycle where a synchronous reset was used to put the circuit into a known state. Rebuild the circuit.
Simulation trace
reset and in are the stimulus applied during each cycle; out is the value observed during that same cycle (it depends on the current in and on what the circuit remembers about the previous cycle’s in):
| Cycle | reset |
in |
out |
|---|---|---|---|
| 1 | 1 | 0 | 0 |
| 2 | 0 | 1 | 1 |
| 3 | 0 | 1 | 0 |
| 4 | 0 | 0 | 0 |
| 5 | 0 | 0 | 0 |
| 6 | 0 | 1 | 1 |
| 7 | 0 | 0 | 0 |
| 8 | 0 | 1 | 1 |
| 9 | 0 | 1 | 0 |
| 10 | 0 | 1 | 0 |
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous, active-high; clears the circuit’s memory of in to 0 |
in |
input | 1 | The signal being watched for rising edges |
out |
output | 1 | Pulses high for one cycle on each rising edge of in |
Notes
- The circuit needs one bit of memory: the value
inheld during the previous cycle. Compare cycle 8 (inrises,out=1) against cycle 9 (instays high,out=0) — the level ofinis not enough to explain the trace, only the transition is. outis a combinational function of the currentinand that one stored bit; only the stored bit is registered.- The VHDL ports are named
in_bit/out_bitsinceinandoutare reserved keywords in VHDL.