A three-input, one-output combinational circuit was simulated for all eight possible input combinations. Study the recorded outputs and rebuild the circuit that produced them.
Simulation trace
sel |
a |
b |
out |
| 0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
0 |
| 0 |
1 |
0 |
1 |
| 0 |
1 |
1 |
1 |
| 1 |
0 |
0 |
0 |
| 1 |
0 |
1 |
1 |
| 1 |
1 |
0 |
0 |
| 1 |
1 |
1 |
1 |
Interface
| Signal |
Direction |
Width |
Description |
sel |
input |
1 |
Selects which data input passes through |
a |
input |
1 |
Data input 0 |
b |
input |
1 |
Data input 1 |
out |
output |
1 |
Matches the recorded trace above |
Notes
- Whenever
sel = 0, out tracks a regardless of b (compare rows 1–4).
- Whenever
sel = 1, out tracks b regardless of a (compare rows 5–8).
- That behavior —
out = sel ? b : a — is exactly a 2-to-1 multiplexer.
- The VHDL output port is named
y instead of out, since out is a reserved keyword in VHDL.