Someone ran a simulation of a mystery 2-input, 1-output combinational circuit and recorded every input combination along with the resulting output. No schematic was saved — only this table. Your job is to figure out which logic function was implemented and rebuild it.
Simulation trace
The circuit has two inputs, a and b, and one output, out. The simulation stepped through every possible input combination and recorded the steady-state output:
| Step | a |
b |
out |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 2 | 1 | 0 | 1 |
| 3 | 1 | 1 | 0 |
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
a |
input | 1 | First operand |
b |
input | 1 | Second operand |
out |
output | 1 | Matches the recorded trace above for every input combination |
Notes
- The output is
1whenever exactly one of the two inputs is1, and0when the inputs agree — that is the definition of the exclusive-or (XOR) function. - This is purely combinational: there is no clock in this circuit.
- The VHDL output port is named
yinstead ofout, sinceoutis a reserved keyword in VHDL.