Infer the Counter — HDLbits.com

A colleague captured the value of a 3-bit output bus, count, across nine consecutive rising clock edges of a mystery circuit, along with the value of a reset input at each edge. The circuit has no other inputs. Reconstruct it.

Simulation trace

reset and count are sampled immediately after each labeled rising edge of clk:

Edge #	`reset`	`count` (after edge)
1	1	000
2	0	001
3	0	010
4	0	011
5	0	100
6	0	101
7	0	110
8	0	111
9	0	000

Interface

Signal	Direction	Width	Description
`clk`	input	1	Clock, rising-edge triggered
`reset`	input	1	Synchronous, active-high
`count`	output	3	Matches the recorded trace above

Notes

When reset is 1 at a rising edge, count becomes 000 on that same edge.
Otherwise, count increments by one on every rising edge.
Edge 8 to edge 9 shows the counter wrapping from 111 back to 000 — a plain 3-bit binary increment does this for free thanks to unsigned overflow, no special-case logic is needed.