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Verilog Language/Modules: Hierarchy

Instantiate Multiple Copies of a Submodule

medium
moduleshierarchyinstantiation

A single-bit submodule can be reused across every bit of a wider bus simply by instantiating it once per bit, each time with a different bit of the vector connected to its ports.

You are given the same 1-bit AND submodule mod_a as before. Build top_module with 4-bit inputs a and b and a 4-bit output out, where out is the bitwise AND of a and b, implemented using four separate instances of mod_a (one per bit position).

Interface

Signal Direction Width Description
a input 4 Operand
b input 4 Operand
out output 4 Bitwise AND of a and b, out[i] = a[i] & b[i]

Notes

  • Each instance needs a unique instance name (e.g. inst0, inst1, …).
  • Connect a[i] and b[i] to the submodule’s inputs, and out[i] to its output, for each i from 0 to 3.
  • This problem is about manual instantiation; the generate construct (a more concise way to do this for larger widths) is covered later in More Language Features.