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Verilog Language/Modules: Hierarchy

Connecting Submodules with an Intermediate Wire

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moduleshierarchywiresinstantiation

When one submodule’s output feeds another submodule’s input, you need a signal in between to carry that connection — this is what internal wires (declared with wire in the enclosing module) are for. Top-level ports cannot be used for this since they only connect to the outside world.

You are given a submodule mod_a that implements an inverter:

module mod_a (
    input in,
    output out
);
    assign out = ~in;
endmodule

Build top_module with input in and output out. Instantiate two copies of mod_a, connecting the output of the first to the input of the second via an internal wire, so that the overall circuit is a double inverter (a buffer): out should equal in.

Interface

Signal Direction Width Description
in input 1 Circuit input
out output 1 Equal to in (double-inverted)

Notes

  • Declare an internal signal with wire mid; before using it.
  • The first instance’s output connects to mid; the second instance’s input also connects to mid.