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Verilog Language/Modules: Hierarchy

Combining Two Different Submodule Types

medium
moduleshierarchyinstantiationaoi

Real designs mix and match different kinds of submodules, not just repeated copies of one. Here you’ll combine two different submodule types to build a small AND-OR-Invert-style structure (without the invert).

You are given two submodules:

module andgate (input in1, input in2, output out);
    assign out = in1 & in2;
endmodule

module orgate (input in1, input in2, output out);
    assign out = in1 | in2;
endmodule

Build top_module with inputs a, b, c, d and output out, computing out = (a AND b) OR (c AND d) using two instances of andgate and one instance of orgate — no direct use of & or | in top_module itself.

Interface

Signal Direction Width Description
a input 1
b input 1
c input 1
d input 1
out output 1 (a AND b) OR (c AND d)

Notes

  • Use two internal wires to carry the two AND results into the OR gate.
  • This mirrors how real hierarchical designs are built from a library of heterogeneous building blocks rather than one repeated part.