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Verilog Language/Procedures

3-to-8 Decoder (case statement)

medium
proceduresalways-blockcasedecoder

The case statement is a cleaner way to express multi-way branches than a long if/else if chain, especially when every branch depends on the exact value of one signal. A decoder β€” which activates exactly one of many outputs based on a binary-encoded input β€” is a textbook use case.

Build a circuit with a 3-bit input in and an 8-bit output out. Exactly one bit of out should be 1: bit number in (the rest should be 0).

Interface

Signal Direction Width Description
in input 3 Binary-encoded index, 0-7
out output 8 One-hot: out[in] = 1, all other bits 0

Examples

in out (binary)
0 00000001
3 00001000
7 10000000

Notes

  • Use always @(*) with a case (in) statement, one branch per value of in (0 through 7).
  • Declare out as output reg since it’s assigned inside a procedural block.