Part-select lets you read out a contiguous range of bits from a vector, written as vector[high:low]. This is one of the most commonly used pieces of Verilog syntax for working with buses.
Build a circuit with a 32-bit input word and a 2-bit input byte_sel, and an 8-bit output byte_out. Depending on byte_sel, output one of the four bytes that make up word.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
word |
input | 32 | Input word |
byte_sel |
input | 2 | Selects which byte of word to output |
byte_out |
output | 8 | Selected byte of word |
Truth Table
| byte_sel | byte_out |
|---|---|
| 0 | word[7:0] |
| 1 | word[15:8] |
| 2 | word[23:16] |
| 3 | word[31:24] |
Notes
- Part-select syntax
word[15:8]extracts an 8-bit slice starting at bit 15 down to bit 8. - Combine part-selects with the ternary operator (or a
caseinside analwaysblock) to choose between them based onbyte_sel.