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Verilog Language/Vectors

Vector Passthrough

easy
vectorsbusesassign

Vectors (multi-bit buses) are declared with a range like [15:0], meaning bit 15 is the most-significant bit and bit 0 is the least-significant bit. Connecting a whole vector is as easy as connecting a single wire.

Build a circuit that connects a 16-bit input in directly to a 16-bit output out.

Interface

Signal Direction Width Description
in input 16 Input vector
out output 16 Output vector, equal to in

Notes

  • A single assign out = in; connects the entire 16-bit bus at once — no bit-by-bit wiring needed as long as both sides are the same width.