HDLbits
Browse Problems

RTL Design Patterns/Branch Prediction

Branch Prediction

Saturating counters, global history, and a gshare predictor.

  1. 1

    CS450 Timer

    Load a 10-bit duration and count down to a sticky terminal-count state.

    medium
  2. 2

    CS450 Two-Bit Saturating Counter

    Implement a two-bit saturating predictor counter with asynchronous reset.

    medium
  3. 3

    CS450 Branch History Register

    Track 32 recent predictions and restore the correct branch history after a misprediction.

    hard
  4. 4

    CS450 Gshare Branch Predictor

    Combine a 7-bit history register with a 128-entry table of two-bit saturating counters.

    hard