- 1easy
Valid/Ready Interface Basics
The foundational valid/ready contract implemented as a pure combinational passthrough — the semantics every later handshaking problem in this track builds on.
- 2medium
Ready/Valid Pipeline Stage
A single registered pipeline slice that correctly propagates valid/ready in both directions, including bubbles and downstream stalls.
- 3hard
Skid Buffer
A two-slot buffer that decouples a registered, purely-state-driven in_ready from same-cycle out_ready — absorbing the one extra beat that 'skids in' after downstream stalls.
- 4hard
Backpressure-Aware FIFO-Fed Pipeline
A small elastic FIFO feeding two registered pipeline stages, demonstrating how sustained backpressure at the output propagates step-by-step all the way back to the input.