Build a D flip-flop with a synchronous, active-high reset and a clock-enable. Both reset and en are only sampled on the rising edge of clk.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous, active-high reset (highest priority) |
en |
input | 1 | Clock enable |
d |
input | 1 | Data input |
q |
output | 1 | Registered output |
Behavior (evaluated on each rising edge of clk)
| reset | en | q (next) |
|---|---|---|
| 1 | x | 0 |
| 0 | 1 | d |
| 0 | 0 | q (hold) |
reset takes priority over en — if both are asserted on the same edge, the flip-flop resets.