Build a 4-bit up/down counter with a synchronous, active-high reset. On each rising edge of clk, the counter either increments or decrements, wrapping around at the 4-bit boundary (15 -> 0 going up, 0 -> 15 going down).
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous, active-high reset to 0 |
up_down |
input | 1 | 1 = count up, 0 = count down |
count |
output | 4 | Current count value |
reset takes priority over up_down on any edge where both matter.