Why multipliers get pipelined
An N x N combinational multiplier’s critical path grows with N, and at any reasonable width it quickly becomes the slowest thing in a datapath. Rather than let it dominate the clock period, real designs (and hardened FPGA DSP blocks) pipeline the multiply across multiple register stages so each stage’s combinational depth is small, letting the whole chip run at a much higher clock frequency at the cost of a few cycles of latency per multiply — exactly the latency-vs-throughput trade explored in the earlier pipeline problems in this category, now applied to real arithmetic.
Structure
This design uses 3 stages, mirroring the way many FPGA hardened multiplier blocks (e.g. a 3-stage-pipelined DSP slice) are commonly configured:
- Stage 1 registers the raw operands
a,b(andvalid). - Stage 2 performs the actual multiply combinationally and registers the result — this is the stage where the real arithmetic work happens; because its inputs are already registered, its own combinational depth is just the multiplier tree, not the multiplier tree plus whatever fed
a/b. - Stage 3 registers the multiply result again, decoupling the multiplier’s output from whatever consumes
productnext (a common technique for timing closure at the multiplier’s output boundary).
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk/rst |
input | — | Clock and synchronous, active-high reset. |
in_valid |
input | 1 | High when a, b are a genuine input this cycle. |
a, b |
input | WIDTH |
Unsigned operands. |
out_valid |
output | 1 | High exactly 3 cycles after the corresponding in_valid. |
product |
output | 2*WIDTH |
a * b from 3 cycles earlier. |
Correctness constraints
productmust equal the exact unsigned producta * bsampled 3 cycles earlier — no truncation (output width is2*WIDTHto hold the full result).out_validmust trackin_validwith exactly 3 cycles of latency, including correctly propagating bubbles.- The pipeline must accept a new
(a, b)pair every cycle with no stalling — 1 multiply result per cycle in steady state despite the 3-cycle latency.