Pipelines

2-Stage Pipeline

The simplest possible pipeline: two register stages with a clean valid/data boundary, always accepting new input every cycle.

4-Stage Pipeline

The 2-stage pipeline concept generalized to STAGES register stages (4 by default), used to reason concretely about how latency scales while throughput stays fixed.

Pipelined Multiplier

A 3-stage pipelined WIDTHxWIDTH multiplier modeled on the classic input-register / multiply-register / output-register structure of a hardened DSP multiplier.

Pipelined Adder (Carry-Select, 2-Stage)

A 2-stage pipelined carry-select adder that splits a wide addition into two halves, speculatively computing both possible upper-half results before the real carry is known.

Latency Matching with Shift Registers

A datapath where an ALU path (1+ cycles of latency) and a passthrough operand must be realigned with a shift register before a downstream combine stage.