Multiplexers select between multiple inputs based on a select signal. The simplest one, a 2-to-1 mux, can be written in a single line using Verilog’s conditional (ternary) operator ?:.
Build a circuit with two data inputs a and b, a select input sel, and an output out. When sel is 0, out should equal a; when sel is 1, out should equal b.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
a |
input | 1 | Data input, selected when sel = 0 |
b |
input | 1 | Data input, selected when sel = 1 |
sel |
input | 1 | Select signal |
out |
output | 1 | Selected data output |
Truth Table
| sel | out |
|---|---|
| 0 | a |
| 1 | b |
Notes
- Use a single
assignstatement with the ternary operator:condition ? value_if_true : value_if_false.