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Verilog Language/More Features

Parity Generator (reduction operators)

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more-featuresreduction-operatorsparityxor

Reduction operators collapse an entire vector down to a single bit by applying an operator between every bit: &data ANDs all bits together, |data ORs them all, and ^data XORs them all. XOR-reduction is exactly the parity function: it is 1 when an odd number of bits in the vector are 1.

Build a circuit with an 8-bit input data and a single-bit output parity, where parity is the XOR of all 8 bits of data (an even-parity bit: appending it to data makes the total number of 1 bits even).

Interface

Signal Direction Width Description
data input 8 Input byte
parity output 1 XOR of all bits of data

Examples

data ones count parity
00000000 0 0
10000000 1 1
11000000 2 0
11100000 3 1

Notes

  • The reduction XOR operator is written as a unary prefix: ^data, not to be confused with the binary XOR operator a ^ b.
  • parity is 1 exactly when data contains an odd number of 1 bits.