Build a decade (mod-10) counter with a synchronous, active-high reset. On each rising edge of clk, the counter advances 0, 1, 2, …, 9, 0, 1, … — it never reaches 10-15.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
reset |
input | 1 | Synchronous, active-high reset to 0 |
q |
output | 4 | Current count, 0-9 |
When the counter reaches 9, the next clock edge wraps it back to 0 instead of continuing to 10.